CMOS Circuits for VCSEL - Based Optical

Electrical IO is becoming limited by copper interconnect channel losses that depend on frequency and distance. Package-to-package optical interconnects see negligible frequency-dependent channel losses, but data rates are limited by the intrinsic optical dynamics and electrical parasitics of the optical devices. This thesis presents 90nm CMOS front-end circuits which apply techniques to operate optical components beyond the intrinsic data rates imposed by these bandwidth limits. The differential TIA is based on a proposed core amplifier which uses cross-coupled NMOS cascodes to increase gain and bandwidth. A symmetric feedback method provides constant gain from DC to 9GHz. The TIA operates at 12.5Gb/s with 260fF input capacitance and 18Gb/s with 90fF input capacitance for an input current of 200uA. The presented VCSEL driver operates a standard commercial GaAs VCSEL at 18Gb/s by using pre-emphasis to compensates for the large capacitance and intrinsic optical dynamics of the VCSEL. The driver derives timing information directly from the full-rate input data and generates pre-emphasis pulses with width resolution less than one bit period in a manner that is compatible with full-rate IO architectures. Because commercial GaAs VCSELs have limited bandwidth but short optical links often have excess link budget, multilevel signaling can be used to increase data rate by increasing the number of bits per symbol instead of increasing the symbol rate. A four-level (PAM-4) VCSEL driver architecture is therefore proposed to transmit at 20Gb/s with lower power consumption than the pre-emphasis driver due to reduced bandwidth requirements. Electrical and optical simulations of the transmitter circuits and behavioral simulations of a PAM-4 receiver and CDR are presented. Thesis Supervisor: Anantha P. Chandrakasan Title: Professor of Electrical Engineering and Computer Science